hdl-design myhdl

Introduction

In this essay, I would like to present the rationale behind MyHDL - a Python-based HDL (hardware description language) that I created.

At a first glance, MyHDL looks like an open source alternative to Verilog and VHDL You can use MyHDL at the register transfer level (RTL) of abstraction for synthesizable code, or at higher levels of abstraction for tasks like system modeling and verification.

I hear you saying: "Why would we need yet another HDL? How can such a project fly without EDA vendor support? This sounds like a crazy idea!" My answer to this is simple and clear - in order to realize the full potential of HDL design, we need a better HDL. Verilog and VHDL are holding us back.

Now don't get me wrong, VHDL and Verilog have served us exceptionally well, but they also have significant issues. Some of these issues are intrinsic to the languages, while others are man-made, but they all work in the same direction - they lead designers, as by an invisible hand, toward low-level coding styles and away from modern practices. Let's briefly consider a number of these issues along with MyHDL's answers to them.

Integer arithmetic

When coding at the RTL level, integer arithmetic is omnipresent. However, Verilog and VHDL make integer arithmetic unnecessarily difficult. The problem is with their RTL type system, which starts from bit vectors and attempts to attach integer-like meanings to them afterwards.

In practice, this concept is broken. For example, mixing "signed" and "unsigned" variables in an expression is notoriously tricky. It gives rise to subtle bugs and you need awkward castings and resizings to make things work.

By comparison, MyHDL starts from integers that work like integers in the first place. Then it allows you to access the bits - if required - according to the standard two's complement representation.

Constant representation

Under the influence of the RTL type system in their HDL, many designers use a bit-level representation for constants. Consequently, RTL code often contains lots of bit strings to represent integer constants and state encodings. Designers seem to think that they have to "help" the poor, easily-confused synthesis tool to get the bits right. Quite obviously, this should be the other way around.

The result is code that is unnecessarily hard to read. Worse yet, bit string representations are a source of subtle bugs. MyHDL puts you on the right track by encouraging human-friendly representations - integer constants in decimal and symbolic state names.

Variables

Variables are one of the best understood programming concepts, and they are supported by both Verilog and VHDL. Nevertheless, even though mainstream HDL design is more than 20 years old, HDL designers still haven't figured out how to use variables properly.

An important factor is Verilog's confusing support and obscure terminology for variables ("blocking assignments"). However, the main problem is man-made. Instead of teaching how to use variables, mainstream Verilog guidelines ban them altogether (in clocked processes). Thus, the confusion is "solved" by brute force amputation.

In reality, local variables work just fine in clocked processes and synthesis supports them without a problem. They can be very useful with regard to writing clearer and more elegant code. Due to a set of mistaken guidelines, many designers remain unaware of these possibilities, and that's a shame.

MyHDL has separate variables and signals, like VHDL, and its signal assignment is more explicit. By making the distinction with signals crystal clear, it encourages the use of variables.

The RTL abstraction

The RTL acronym stands for "Register Transfer Level". It suggests describing behavior at clock ticks. Therefore, the natural computational model for RTL consists of a set of cooperating clocked processes. This is an ideal abstraction level - clearly defined, and fully supported by efficient synthesis.

Unfortunately, designers are encouraged to think at a lower level of abstraction. As discussed above, common guidelines work against clocked processes. Consequently, many designers describe all behavior in a combinatorial process with an auxiliary clocked process just for the registers. The resulting code is bulkier than necessary as you now have two processes and two signals per register instead of one. Moreover, combinatorial processes have potential issues not found in clocked processes.

Textbooks don't help. Typically, they spend a lot of pages explaining how to describe an AND gate, a MUX (multiplexer), a full adder, and a flip-flop (register). But these building blocks are the output of RTL synthesis. What should be taught instead is how to think in terms of behavior at clock ticks and how to write code for efficient synthesis.

MyHDL encourages true RTL modeling with clocked processes. As a unique feature, it has a process type that infers the reset functionality automatically, so that the designer can concentrate on describing functional behavior.

Modern coding practices

Professional HDL designers spend a lot of time with code. The analogies with software development are obvious (and beautiful). Yet, merely mentioning the usefulness of a software perspective on HDL design is sufficient to trigger irrational negative reactions. You don't have to look very far to see evidence of this.

As a result, many hardware designers remain blind to potentially useful developments in the software domain. Test-driven hardware design? Never heard of. Agile hardware development? Doesn't exist, even though FPGAs are the ideal platform to enable such a methodology.

The main cause for this problem is not with HDLs, but with the unfortunate attitude of denying the obvious analogy with software. Still, traditional HDLs don't help, as they are designed according to relatively old paradigms.

MyHDL is different as it is based on Python, which is arguably one of the most successful modern programming languages. With MyHDL, using modern software development techniques is natural and straightforward, thanks to its Python foundation. Such techniques are especially useful for verification.

Conclusion

In this essay I have only briefly glanced over a number of topics. However, remember that everything I said is backed by a real HDL that works. MyHDL is not yet the major force in "design land," but it has been and is being used for all kinds of applications, including high volume ASICs. If you would like to get started now, go to the MyHDL website where you will find a manual, examples, tutorials, and installation instructions that will allow you to quickly get up to speed.