Chisel HDL: the latest instance of a flawed approach   19-Oct-2015

hdl-design

It's a simulation language!   02-Sep-2014

hdl-design myhdl

Thinking software at the RTL level   08-Jun-2014

At the RTL level, "thinking hardware" is a suboptimal strategy. The right approach is to use a "software perspective".

hdl-design myhdl

Why HDL designers should learn Python   25-Mar-2014

Python is an ideal language for writing reference models.

hdl-design myhdl

Why do we need signal assignments?   19-Feb-2014

Many designers incorrectly believe that signal assignments are required to model concurrency. This essay explains what the real reason is.

hdl-design myhdl

The Case for a Better HDL   25-Dec-2013

VHDL and Verilog have served us exceptionally well, but they also have significant issues. In order to realize the full potential of HDL design, we need a better HDL.

hdl-design myhdl

MyHDL-based design of a digital macro   01-Mar-2010

The story behind the first ASIC designed with MyHDL.

hdl-design myhdl

These Int's Are Made for Countin'   01-Mar-2009

Why Verilog and VHDL have it wrong on integers, and how MyHDL does it right.

hdl-design myhdl